A transmission apparatus for transmitting frame signals is attached to a communication network. The transmission apparatus multiplexes or demultiplexes frame signals into frame signals of another format, or adds or drops frame signals to or from frame signals of another format. The frame signals will hereinafter be referred to simply as “frames.”
FIG. 1 is a diagram illustrating a configuration example of a transmission apparatus. The transmission apparatus 1 includes a client line interface unit 2 and network line interface units 3-E and 3-W. In the description and drawings given hereinafter, the line interface units will each be designated as LIU.
The client LIU 2 receives a frame from a client apparatus connected to a local area network, and transfers the frame to the network LIU 3-E or 3-W according to the destination of the frame.
The network LIU 3-E is responsible for transmitting a frame transferred from the network LIU 3-W onto a wide area network, and for adding a frame received from the client LIU 2 onto a frame suitable for transmission to the wide area network. The network LIU 3-E is also responsible for transferring to the client LIU 2 a frame created by dropping a signal stored in a frame received from the wide area network.
The network LIU 3-W is responsible for transmitting a frame transferred from the network LIU 3-E onto a wide area network, and for adding a frame received from the client LIU 2 onto a frame suitable for transmission to the wide area network. The network LIU 3-W is also responsible for transferring to the client LIU 2 a frame created by dropping a signal stored in a frame received from the wide area network.
For example, the client LIU 2 may map an asynchronous frame received from the local area network into an ODUk frame and transfer the ODUk frame to the network LIU 3-E or 3-W. The network LIU 3-E or 3-W may map the ODUk frame received from the client LIU 2 into a higher-speed OTU frame, thereby adding the ODUk frame onto the OTU frame for transmission to the wide area network. Further, the network LIU 3-E or 3-W may drop an ODUk frame from an OTU frame received from the wide area network and transfer the ODUk frame to the client LIU 2.
FIG. 2 is a diagram illustrating a configuration example of the client LIU 2 depicted in FIG. 1. The client LIU 2 includes an optical transmitting/receiving unit 10, a mapping unit 11, a demapping unit 12, and a cross-connect unit 13.
The optical transmitting/receiving unit 10 receives a frame transmitted from the client apparatus via a local area network and converts it into an electrical signal. The mapping unit 11 maps a client signal stored in the received frame into a synchronous frame. The cross-connect unit 13 forms a cross-connect for transferring the synchronous frame to one or the other of the network LIUs 3-E and 3-W according to the destination of the client signal.
The cross-connect unit 13 also forms a cross-connect for directing to the demapping unit 12 a synchronous frame to be transferred from the network LIU 3-E or 3-W to the client LIU 2. The demapping unit 12 demaps the synchronous frame to extract a signal to be transmitted to the client and passes the extracted signal to the optical transmitting/receiving unit 10. The optical transmitting/receiving unit 10 converts the extracted signal into an optical signal and transmits it to the local area network.
FIG. 3 is a diagram illustrating a configuration example of the network LIU 3-E depicted in FIG. 1. The network LIU 3-W has substantially the same configuration. The network LIU 3-E includes a cross-connect unit 15, a framer 16, an optical transmitting/receiving unit 17, and a deframer 18.
The cross-connect unit 15 forms a cross-connect for transferring the synchronous frame received from the client LIU 2 to the framer 16. The cross-connect unit 15 also forms a cross-connect for receiving a synchronous frame from the network LIU 3-W or transferring a synchronous frame to the network LIU 3-W.
The framer 16 maps the synchronous frame received from the client LIU 2 into a higher-speed synchronous frame for transmission to the wide area network. The optical transmitting/receiving unit 17 converts the synchronous frame generated by the framer 16 into an optical signal and transmits it to the wide area network.
The deframer 18 demaps a frame that the optical transmitting/receiving unit 17 received from the wide area network into a lower-speed synchronous frame. The cross-connect unit 15 forms a cross-connect for transferring the demapped synchronous frame to the client LIU 2.
The mapping unit 11, demapping unit 12, framer 16, and deframer 18 described above are each equipped with a stuffing control unit for controlling of stuffing inserted in an output frame. The stuffing control unit determines the amount of stuffing inserted in the output frame and the position of insertion in accordance with the speed difference between the input data and the output data.
FIG. 4 is a diagram illustrating a configuration example of the mapping unit 11 equipped with such a stuffing control unit. The mapping unit 11 includes a frame detection unit 20, a stuffing control unit 21, and a frame generating unit 22. The demapping unit 12, the framer 16, and the deframer 18 may each be equipped with a stuffing control unit similar to the stuffing control unit 21 described hereinafter.
The frame detection unit 20 detects or synchronously detects an input frame, and supplies the stuffing control unit 21 with a timing signal that indicates the timing that the information to be stored in the output frame is input from among the information stored in the input frame.
The stuffing control unit 21 includes a FIFO (first-in, first-out) memory 23, such as an elastic store memory, and a FIFO controller 24. The FIFO controller 24 generates, based on the timing signal received from the frame detection unit 20, a write enable signal for writing the input frame to the FIFO memory 23, and generates a write address based on the write enable signal.
Further, the FIFO controller 24 generates a read address for reading transmit data from the FIFO memory 23. When generating the read address, the FIFO controller 24 controls the amount of stuffing to be inserted and the position of insertion by adjusting the generation of a read enable signal, based on the speed difference between the input data and the output data and on the amount of generation of the write enable signal.
The frame generating unit 22 stores the data read out by the stuffing control unit 21 into a synchronous frame.
The payload of the synchronous frame is divided into data storage areas referred to as “slots” each for carrying a prescribed amount of data. Each slot is used as the smallest unit of storage area to which one client signal is mapped. An example of such a slot is the “tributary slot” used in the OPU (Optical channel payload unit) k format standardized by the ITU-T (International Telecommunication Union Telecommunication Standardization Sector). FIG. 5 is an explanatory diagram of the tributary slot.
The OPUk frame includes an overhead area and a payload area. The overhead area has a frame size of 16 bytes×4 rows in the first to 16th columns. The payload area has a frame size of 3808 bytes×4 rows in the 17th to 3824th columns.
FIG. 5 illustrates an example of a frame format in which the payload area is divided into 80 tributary slots TS1 to TS80. The 17th column, the 97th column, the 177th column, etc., are used for the tributary slot TS1. On the other hand, the 18th column, the 98th column, the 178th column, etc., are used for the tributary slot TS2. Likewise, the 19th column, the 99th column, the 179th column, etc., are used for the tributary slot TS3, and the 96th column, the 176th column, the 256th column, etc., are used for the tributary slot TS80.
FIG. 6 is a diagram illustrating a prior art configuration example of the stuffing control unit 21 depicted in FIG. 4. Read/write to the FIFO memory and the insertion of stuffing are performed on a slot-by-slot basis so that a different client signal can be stored in each slot. In the configuration example illustrated in FIG. 6, it is assumed that the payload area is divided into n slots.
The stuffing control unit 21 includes first to n-th FIFOs 23-1 to 23-n , first to n-th write address generators 25-1 to 25-n , and first to n-th Cm calculators 26-1 to 26-n . The stuffing control unit 21 further includes first to n-th read enable generators 27-1 to 27-n and first to n-th read address generators 28-1 to 28-n.
The first to n-th FIFOs 23-1 to 23-n respectively store the client signals to be stored in the first to n-th slots of the output frame. The client signals stored in the first to n-th slots will be designated as the first to n-th client signals, respectively.
The first to n-th write address generators 25-1 to 25-n respectively take as inputs the write enable signals WEN1 to WENn, generated based on the timing signal received from the frame detection unit 20, for writing the first to n-th client signals to the first to n-th FIFOs 23-1 to 23-n , respectively.
Based on the write enable signals WEN1 to WENn, the first to n-th write address generators 25-1 to 25-n respectively generate the write addresses for writing the first to n-th client signals. The first to n-th write address generators 25-1 to 25-n respectively specify the write addresses in the first to n-th FIFOs 23-1 to 23-n by the thus generated addresses.
The first to n-th Cm calculators 26-1 to 26-n respectively receive the write enable signals WEN1 to WENn as inputs. The first to n-th Cm calculators 26-1 to 26-n count the number of occurrences of the respective write enable signals WEN1 to WENn. In the following description, a count of the number of occurrences of the write enable signal may be referred to as the “Cm value.” The first to n-th Cm calculators 26-1 to 26-n supply the calculated Cm values to the first to n-th read enable generators 27-1 to 27-n.
Based on the respectively received Cm values and the speed differences between the input data and the output data, the first to n-th read enable generators 27-1 to 27-n each determine the amount of stuffing inserted and the position of insertion.
The first to n-th read enable generators 27-1 to 27-n may each determine the amount of stuffing inserted and the position of the insertion by using, for example, GMP operations in accordance with the generic mapping procedure (GMP). Based on the thus determined stuffing insertion positions, the first to n-th read enable generators 27-1 to 27-n respectively generate the read enable signals for reading the first to n-th client signals from the first to n-th FIFOs 23-1 to 23-n . The first to n-th read enable generators 27-1 to 27-n supply the read enable signals to the first to n-th read address generators 28-1 to 28-n , respectively.
Based on the received read enable signals, the first to n-th read address generators 28-1 to 28-n respectively generate the read addresses for reading the first to n-th client signals.
In the above stuffing control unit 21, the control signals for controlling read/write operations on the first to n-th FIFOs 23-1 to 23-n may be shared among different slots. Such control signals include, for example, the write enable signal, write address, Cm value, read enable signal, and read address.
For example, in the above GMP, one client signal can be mapped into a plurality of tributary slots. In the following description, a group of slots for one repeat cycle of the slot numbers within one frame will be referred to as the “repeating unit group.” For example, in the frame format example of FIG. 5, the tributary slots TS1 to TS80 in the 17th to 96th columns form one repeating unit group, and the tributary slots TS1 to TS80 in the 97th to 176th columns form another repeating unit group.
Further, a group made up of a plurality of slots transporting the same client signal will be referred to as the “slot group.” When mapping one client signal into a plurality of tributary slots, the stuffing insertion position is controlled so that each slot belonging to the same slot group within the same repeating unit group either contains all data or contains all stuffing. That is, the stuffing insertion position is synchronized among the tributary slots belonging to the same slot group.
In order to synchronize the stuffing insertion position among the plurality of slots belonging to the same slot group, the stuffing control unit 21 uses a signal distribution circuit which is configured to distribute the control signal generated for one of the slots in one slot group to the other slots belonging to the same slot group. More specifically, the signal distribution circuit has n pairs of input/output lines (n is a natural number), and is configured so that when the n pairs of input/output lines are divided into groups, an input signal to one of the input lines in each group is distributed to all the output lines belonging to the same group. As an example, a description will be given below for the case where the Cm value is distributed.
FIG. 7 is a diagram illustrating a prior art signal distribution circuit for distributing the Cm value. The signal distribution circuit includes selectors 29-2 to 29-n . The selectors 29-2 to 29-n each take, as first to n-th inputs, the Cm values Cm1 to Cmn calculated by the first to n-th Cm calculators 26-1 to 26-n , respectively. In the description and drawings given hereinafter, the “selector” may be designated as SEL.
Each of the selectors 29-2 to 29-n selects one of the Cm values Cm1 to Cmn under the control of member specifying information MN and master specifying information MS, and supplies the selected Cm value to a corresponding one of the second to n-th read enable generators 27-2 to 27-n. The first read enable generator 27-1 is supplied with the Cm value Cm1 calculated by the first Cm calculator 26-1.
The member specifying information MN specifies the slots belonging to each slot group. FIG. 8 is a diagram illustrating an example of the format of the member specifying information MN. The illustrated example depicts the format of the member specifying information MN for the case where the upper limit number of tributary slots is 80. The high-order ((i−1)×80+1)th to (i×80)th bits of the member specifying information MN carry information for the i-th tributary slot.
If the value of the high-order ((i−1)×80+j)th bit is “1”, it indicates that the j-th tributary slot belongs to the same slot group as the i-th tributary slot. If the value of the high-order ((i−1)×80+j)th bit is “1”, it indicates that the j-th tributary slot belongs to a slot group other than the i-th tributary slot.
In the illustrated example, the tributary slots TS5, TS8, and TS79 belong to the same slot group as the tributary slot TS1. The tributary slots TS7 and TS80 belong to the same slot group as the tributary slot TS4.
FIG. 9 is a diagram illustrating an example of the format of the master specifying information MS. The master specifying information MS specifies the master slot in each slot group. The signal distribution circuit distributes the control signal input for the master slot to the other slots in the same slot group. The slots other than the master slot may be designated as “slave slots.”
The illustrated example depicts the format of the master specifying information MS for the case where the upper limit number of tributary slots is 80. If the value of the high-order i-th bit is “1”, the i-th slot is the master slot. If the value of the high-order i-th bit is “0”, the i-th slot is a slave slot. In the illustrated example, the tributary slots TS1, TS4, and TS9 are specified as the master slots.
Reference is made to FIG. 7. When the master specifying information MS specifies the i-th slot as the master slot, the SEL 29-i (i is an integer between 2 and n) selects Cmi for output to the i-th read enable generator 27-i.
If the i-th slot is a slave slot, the SEL 29-i selects for output to the i-th read enable generator 27-i the Cm value Cmj calculated for the j-th slot which is the master slot belonging to the same slot group as the i-th slot.
In the prior art, a selector circuit has been proposed that can drastically reduce the amount of circuitry when reading data of a plurality of words from a plurality of data. This selector circuit includes: a pointer counter which outputs pointer data pointing to data to be read out; a data selection circuit which, based on the pointer data from the pointer counter, generates pointer values indicating the starting positions of the data to be read out, the number of pointer values being equal to the number of words; a front-end selector array which is constructed from as many selectors as the number of words and which outputs data that are divided between the selectors and are selected based on the pointer values from the data selection circuit; an order selection circuit for selecting the order in which the selected data are to be read out based on the pointer data from the pointer counter; and a back-end selector 2 which receives the selected data from the front-end selector array and outputs the selected data by reordering the data in accordance with an output from the order selection circuit.
Related art is disclosed in Japanese Laid-open Patent Publication No. 2004-62588.